The present subject matter relates to a duty correction circuit, and more particularly, to a duty correction circuit for increasing a duty ratio sensing speed as occasion demands.
A duty ratio is a ratio of a pulse width to a pulse cycle of a clock. A clock having a duty ratio of 50% is generally used in digital clock application fields such as a semiconductor integrated circuit. The duty ratio of 50% means that a width of a high level clock period is identical to a width of a low level clock period. The duty correction circuit corrects a duty ratio of a clock to be a duty ratio of 50% if an input clock has an incorrect duty ratio.
In the digital clock application fields, it is important to precisely control the duty ratio of a clock. If the duty ratio of a clock is not accurately controlled in a synchronous semiconductor device that synchronizes with a clock to input and output data, data may be distorted. Lately, a double data rate (DDR) synchronous semiconductor device has been used in order to increase an operation speed. A double data rate (DDR) scheme enables a semiconductor device to input and output data not only at a rising edge of a clock but also at a falling edge. Therefore, the duty ratio is more important in a DDR synchronous semiconductor device to secure a data margin.
FIG. 1 is a diagram illustrating a duty correction circuit according to the prior art.
Referring to FIG. 1, the duty correction circuit according to the prior art includes a duty ratio sensor 101 and a duty ratio corrector 103.
Still referring to FIG. 1, the duty ratio sensor 101 includes a charging/discharging unit 105, first and second charge storing units 107 and 109, a reset unit 111, and an activator 113. The charging/discharging unit 105 charges or discharges the first and second charge storing units 107 and 109 according to a duty ratio of a clock CLKOUT and a complementary clock CLKOUTB, which are fed back from the duty ratio corrector 103 and generates a first and a second correction signals A and B. The first and second charge storing units 107 and 109 are connected to an output end of the duty ratio sensor 101 and charged or discharged thereby. The first and second charge storing units 107 and 109 control a logical level transition speed of the first and second correction signals A and B. The reset unit 111 resets the first and second correction signals A and B to a high level in response to a sensing signal EN. The activator 113 activates the duty ratio sensor 101 in response to the sensing signal EN.
When the sensing signal EN is enabled to a high level, a transistor of the activator 113 is turned on and the duty ratio sensor 101 starts operating thereby. Since the reset unit 111 is turned on before the sensing signal EN is initially enabled to a high level, both of the first and second correction signals A and B are high level signals.
The duty ratio corrector 103 operates in response to level transition of the first and second signals A and B. Therefore, once the sensing signal EN is enabled, the sensing signal EN sustains the enable state continuously. However, if the duty ratio corrector 103 operates according to whether the first and second correction signals A and B are shifted to the opposite level or not, the sensing signal EN is regularly enabled and the duty ratio sensor 101 is reset by the reset unit 111. Since the duty ratio is corrected by determining whether a level is shifted or not, it is required to reset the first and second charge storing units 107 and 109 continuously in order to shift the levels of the first and second corrections again.
The reset unit 111 is turned off in an enable period of the sensing signal EN. If the clock CLKOUT is inputted as a high level, an NMOS transistor T1 receiving the clock CLKOUT is turned on. Also, an NMOS transistor T2 connected in serial is turned on because a drain voltage of the NMOS transistor T1 is dropped. Therefore, the first correction signal A transits to a low level. However, the first correction signal A gradually transits because the first charge storing unit 107 does not let the correction signal A to abruptly transit.
The complementary clock CLKOUTB has an opposite level to the clock CLKOUT. That is, the complementary clock CLKOUTB has a low level during a high level period of the clock CLKOUT. If the complementary clock CLKOUTB is inputted with a low level, an NMOS transistor T3 receiving the complementary clock CLKOUTB is not turned on and the second correction signal B is not changed.
If the complementary clock CLKOUTB is inputted with a high level, the NMOS transistor T3 receiving the complementary clock CLKOUTB and an NMOS transistor T4 connected to T3 in series are turned on. Although the second correction signal B transits to a low level, the level thereof gradually falls by the second charge storing unit 109.
If the duty ratio of the clock CLKOUT and the complementary clock CLKOUTB is not 50%, the logical level transition of the first correction signal A becomes different from that of the second correction signal B. If the low level period of the clock CLKOUT is wider than the high level period thereof, the logical level of the second correction signal B is dropped more by the complementary clock CLKOUTB. Then, the second correction signal B turns on a PMOS transistor T5 of the charging/discharging unit 105 and the first correction signal A rises to a high level. Finally, the first and second signals A and B are shifted to inverted levels due to the duty ratio difference between the clock CLKOUT and the complementary clock CLKOUTB.
The duty ratio corrector 103 includes NMOS transistors T9 and T7 for receiving a clock CLKIN and a complementary clock CLKINB respectively and PMOS transistors T6 and T8 receiving the first and second correction signals A and B respectively. The NMOS transistors T9 and T7 and the PMOS transistors T6 and T8 are connected in serial. Here, the transistor T8 receiving the first correction signal A is connected to the transistor T7 receiving a complementary clock and the transistor T6 receiving the second correction signal B is connected to the transistor T9 receiving an clock CLKIN.
The first and second correction signals A and B may have different levels according to the duty ratio. Such a difference can turn on the NMOS transistors T6 and T8. For example, as shown in FIG. 1, the first correction signal A transits to a high level and the second correction signal B transits to a low level due to a wide low level period of the clock CLKIN. Therefore, the NMOS transistor T8 receiving the first correction signal A is turned on strongly in process of time, and the NMOS transistor T6 receiving the second correction signal B is turned on weakly in process of time.
If the transistors T6 and T8 receiving the first and second correction signals A and B are not included, the complementary clock CLKOUTB is outputted by receiving the clock CLKIN, and the clock CLKOUT is outputted by receiving the complementary clock CLKINB. However, the high level period of the clock CLKOUT extends because the first correction signal A turns on the transistor T8 strongly. And, the low level period of the complementary clock CLKOUTB extends because the second correction signal B turns on the transistor T6 weakly.
Therefore, a complementary clock output end and a clock output end output the complementary clock CLKOUTB and the clock CLKOUT with duty ratio corrected although the complementary clock output received an clock CLKIN having a wide low level period and outputted a complementary clock CLKOUTB and the clock output end received a complementary clock having a wide high level period and outputted the clock CLKOUT having the extended wide low level period.
It is required to correct a duty ratio fast in a particular mode such as a self-refresh mode or a power-up mode of a DRAM, compared with a normal mode. It is important to sustain system performance.
However, the duty correction circuit according to the prior art corrects the duty ratio at a uniform speed. That is, a speed of duty ratio correction is identical not only in a normal mode but also in a particular mode such as a power up mode or a self refresh mode.
If the duty ratio correction speed is set to be high for the self-refresh mode or the power-up mode, a time for correcting a duty ratio can be reduced. However, the high duty ratio correction speed may cause high jitter and increase instability of a system because the high duty ratio correction speed increases a clocking speed even in a normal mode which does not require the high duty ratio correction speed.